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PDF ( 数据手册 , 数据表 ) UPD70F3370A

零件编号 UPD70F3370A
描述 32-bit Single-Chip Microcontroller
制造商 NEC
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UPD70F3370A 数据手册, 描述, 功能
Data Sheet
V850ES/FE3
32-bit Single-Chip Microcontroller
Hardware
µPD70F3370A(A) µPD70F3371(A)
µPD70F3370A(A1) µPD70F3371(A1)
µPD70F3370A(A2) µPD70F3371(A2)
Document No. U18564EE1V2DS00
Date Published March 2008
© NEC Electronics 2008
Printed in Germany







UPD70F3370A pdf, 数据表
V850ES/FE3
Table of Contents
5. Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.1 Package Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.2 Product Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.2.1 Marking of pin 1 at a QFP (Quad Flat Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.2.2 Identification of Lead-Free Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6. Change History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
8 Data Sheet U18564EE1V2DS00







UPD70F3370A equivalent, schematic
V850ES/FE3
2.6 DC Characteristics
2.6.1 Input/Output Level
(Ta = -40 to +85°C, C=4.7uF, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V)
Parameter
Sym-
bol
Conditions
MIN.
TYP.
MAX.
Uni
t
VIH1
Pin Group 1B
0.7EVDD
EVDD V
High level
VIH2
Pin Group 1D
Pin Group 2D
0.8EVDD
0.8EVDD
EVDD
EVDD
V
V
input voltage VIH3
Pin Group 2A
0.7EVDD
EVDD V
VIH4
Pin Group 4
0.7AVREF0
AVREF0 V
VIH5
Pin Group 6
0.8EVDD
EVDD V
VIL1
Pin Group 1B
EVSS
0.3EVDD V
Low level
VIL2
Pin Group 1D
Pin Group 2D
EVSS
EVSS
0.4EVDD V
0.4EVDD V
input voltage VIL3
Pin Group 2A
EVSS
0.3EVDD V
VIL4
Pin Group 4
AVSS
0.3AVREF0 V
VIL5
Pin Group 6
EVSS
0.2EVDD V
VHYS1
Pin
Group
1B
Center point at
0.5 x EVDD Note3
0.267 x EVDD - 0.51V
V
Input hysteresis
VHYS2
Pin
Pin
Group
Group
1D
2D
Center point at
0.6 x EVDD Note3
Center point at
0.6 x EVDD Note3
0.192 x EVDD - 0.31V
0.192 x EVDD - 0.31V
V
V
VHYS5
Pin Group 6
Center point at
0.5 x EVDD Note3
0.535 x EVDD - 0.9V
V
High level
output voltage
Note2
VOH1
Pin Group
1x, 2x
VOH3 Pin Group 4
IOH=-1.0mA
IOH=-100uA
IOH=-1.0mA
IOH=-100uA
EVDD-1.0
EVDD-0.5
AVREF0-1.0
AVREF0-0.5
EVDD
EVDD
AVREF0
AVREF0
V
V
V
V
Low level output
voltageNote2
Pin Group 1x,
VOL1
2x
P914, 915
IOL=1.0mA
IOL=3.0mA
0
0.4 V
VOL3 Pin Group 4 IOL=1.0mA
0
0.4 V
Software pull-up
resistor
R1
VI=0V
10 30 100 kΩ
Software Note1
pull-down resistor
R2
VI=VDD
10 30 100 kΩ
Remark: The characteristics of the dual-function pins are the same as those of the port pins unless
otherwise specified.
Notes: 1.
2.
3.
DRST terminal only. (Control register is OCDM)
Total IOH/IOL max is 20mA/-20mA each power supply line (EVDD and AVREF0).
AVREF0 IOH/IOL current is excluding ADC0 current IAREF0.
Typical value. Not tested and guaranteed
16 Data Sheet U18564EE1V2DS00










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