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PDF ( 数据手册 , 数据表 ) SiHF9630S
| 零件编号 | SiHF9630S | ||
| 描述 | Power MOSFET ( Transistor ) | ||
| 制造商 | Vishay | ||
| LOGO |  |
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1 Page
Power MOSFET
IRF9630S, SiHF9630S
Vishay Siliconix
PRODUCT SUMMARY
VDS (V)
RDS(on) ()
Qg (Max.) (nC)
Qgs (nC)
Qgd (nC)
Configuration
- 200
VGS = - 10 V
29
5.4
15
Single
0.80
D2PAK (TO-263)
S
G
GD
S
D
P-Channel MOSFET
ORDERING INFORMATION
Package
Lead (Pb)-free and Halogen-free
Lead (Pb)-free
Note
a. See device orientation.
D2PAK (TO263)
SiHF9630S-GE3
IRF9630SPbF
SiHF9630S-E3
FEATURES
• Halogen-free According to IEC 61249-2-21
Definition
• Surface Mount
• Available in Tape and Reel
• Dynamic dV/dt Rating
• Repetitive Avalanche Rated
• P-Channel
• Fast Switching
• Ease of Paralleling
• Compliant to RoHS Directive 2002/95/EC
DESCRIPTION
Third generation Power MOSFETs from Vishay provide the
designer with the best combination of fast switching,
ruggedized device design, low on-resistance and
cost-effectiveness.
The D2PAK (TO263) is a surface mount power package
capable of accommodating die size up to HEX-4. It provides
the highest power capability and the lowest possible
on-resistance in any existing surface mount package. The
D2PAK (TO263) is suitable for high current applications
because of its low internal connection resistance and can
dissipate up to 2.0 W in a typical surface mount application.
D2PAK (TO263)
SiHF9630STRL-GE3a
IRF9630STRLPbFa
SiHF9630STL-E3a
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current
Pulsed Drain Currenta
Linear Derating Factor
Linear Derating Factor (PCB Mount)e
Single Pulse Avalanche Energyb
Avalanche Currenta
Repetiitive Avalanche Energya
Maximum Power Dissipation
Maximum Power Dissipation (PCB Mount)e
Peak Diode Recovery dV/dtc
VGS at - 10 V
TC = 25 °C
TC = 100 °C
VDS
VGS
ID
IDM
TC = 25 °C
TA = 25 °C
EAS
IAR
EAR
PD
dV/dt
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)
for 10 s
TJ, Tstg
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. VDD = - 50 V, starting TJ = 25 °C, L = 17 mH, Rg = 25 , IAS = - 6.5 A (see fig. 12).
c. ISD - 6.5 A, dI/dt 120 A/μs, VDD VDS, TJ 150 °C.
d. 1.6 mm from case.
e. When mounted on 1" square PCB (FR-4 or G-10 material).
LIMIT
- 200
± 20
- 6.5
- 4.0
- 26
0.59
0.025
500
- 6.4
7.4
74
3.0
- 5.0
- 55 to + 150
300d
UNIT
V
A
W/°C
mJ
A
mJ
W
V/ns
°C
* Pb containing terminations are not RoHS compliant, exemptions may apply
Document Number: 91085
S11-1051-Rev. C, 30-May-11
www.vishay.com
1
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
 
Package Information
Vishay Siliconix
TO-263AB (HIGH VOLTAGE)
(Datum A)
4 L1
34
E
4
A
A
AB
c2
D5
H
CC
123
L2
BB
Detail A
2xe
2 x b2
2xb
0.010 M A M B
Plating
(c)
A
c
± 0.004 M B
5
b1, b3
Base
metal
c1 5
Gauge
plane
0° to 8°
H
B
Seating plane
L3 L L4
A1
Detail “A”
Rotated 90° CW
scale 8:1
E
D1 4
Lead tip
(b, b2)
Section B - B and C - C
Scale: none
E1
View A - A
4
MILLIMETERS
INCHES
MILLIMETERS
INCHES
DIM.
MIN.
MAX.
MIN.
MAX.
DIM.
MIN.
MAX.
MIN.
MAX.
A
4.06
4.83
0.160
0.190
D1 6.86
- 0.270 -
A1
0.00
0.25
0.000
0.010
E
9.65
10.67
0.380
0.420
b
0.51
0.99
0.020
0.039
E1 6.22
- 0.245 -
b1
0.51
0.89
0.020
0.035
e 2.54 BSC
0.100 BSC
b2
1.14
1.78
0.045
0.070
H
14.61
15.88
0.575
0.625
b3
1.14
1.73
0.045
0.068
L
1.78
2.79
0.070
0.110
c
0.38
0.74
0.015
0.029
L1 - 1.65 - 0.066
c1
0.38
0.58
0.015
0.023
L2 - 1.78 - 0.070
c2
1.14
1.65
0.045
0.065
L3 0.25 BSC
0.010 BSC
D
8.38
9.65
0.330
0.380
L4
4.78
5.28
0.188
0.208
ECN: S-82110-Rev. A, 15-Sep-08
DWG: 5970
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimensions are shown in millimeters (inches).
3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the
outmost extremes of the plastic body at datum A.
4. Thermal PAD contour optional within dimension E, L1, D1 and E1.
5. Dimension b1 and c1 apply to base metal only.
6. Datum A and B to be determined at datum plane H.
7. Outline conforms to JEDEC outline to TO-263AB.
Document Number: 91364
Revision: 15-Sep-08
www.vishay.com
1
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| 页数 | 9 页 | ||
| 下载 | [ SiHF9630S.PDF 数据手册 ] | ||
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