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PDF ( 数据手册 , 数据表 ) TDA8035

零件编号 TDA8035
描述 High integrated and low power smart card interface
制造商 NXP Semiconductors
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TDA8035 数据手册, 描述, 功能
TDA8035
High integrated and low power smart card interface
Rev. 3.0 — 25 June 2014
Product data sheet
COMPANY PUBLIC
1. General description
The TDA8035 is the cost efficient successor of the established integrated contact smart
card reader IC TDA8024. It offers a high level of security for the card by performing
current limitation, short-circuit detection, ESD protection as well as supply supervision.
The current consumption during the standby mode of the contact reader is very low as it
operates in the 3 V supply domain. The TDA8035 is therefore the ideal component for a
power efficient contact reader.
2. Features and benefits
2.1 Protection of the contact smart card
Thermal and short-circuit protection on all card contacts
VCC regulation:
5 V, 3 V, 1.8 V 5 % on 2 220 nF multilayer ceramic capacitors with low ESR
Current spikes of 40 nA/s (VCC = 5 V and 3 V) or 15 nA/s (VCC = 1.8 V) up to
20 MHz, with controlled rise and fall times. Filtered overload detection is
approximately 120 mA.
Automatic activation and deactivation sequences initiated by software or by hardware
in the event of a short-circuit, card take-off, overheating, falling VREG VDD(INTF),VDDP
Enhanced card-side ElectroStatic Discharge (ESD) protection of (> 8 kV)
Supply supervisor for killing spikes during power on and off:
threshold internally fixed
externally by a resistor bridge
2.2 Easy integration into your contact reader
SW compatible to TDA8024 and TDA8034
5 V, 3 V, 1.8 V smart card supply
DC-to-DC converter for VCC generation separately powered from 2.7 V to 5.5 V supply
(VDDP and GNDP)
Very low power consumption in Deep Shutdown mode
Three protected half-duplex bidirectional buffered I/O lines (C4, C7 and C8)
External clock input up to 26 MHz
Card clock generation up to 20 MHz using pins CLKDIV1 and CLKDIV2 with
synchronous frequency changes of fXTAL, fXTAL/2, fXTAL/4 or fXTAL/8
Non-inverted control of pin RST using pin RSTIN
Built-in debouncing on card presence contact







TDA8035 pdf, 数据表
NXP Semiconductors
8.2 Voltage supervisor
TDA8035
High integrated and low power smart card interface
VREG
VDDP
Deep_shutdown
vbg
VREG
VDD(INTF)
Poradj
vbg
vbg
001aan747
Fig 3. Block voltage supervisor
The voltage supervisor is used as a power-on reset, and also as supply drop detection
during a card session. The threshold of the voltage supervisor is set internally in the IC for
VDDP and VREG. The threshold can be adjusted externally for VDD(INTF) using the
PORADJ pin. As long as VREG is less than Vth(VREG) + Vhys(VREG), the IC remains inactive
whatever the levels on the command lines are. The inactivity lasts for the duration of tw
after VREG has reached a level higher than Vth(VREG) + Vhys(VREG). The outputs of the
VDDP, VREG and VDD(INTF) supervisors are combined and sent to a digital controller in
order to reset the TDA8035. The reset pulse of approximately 5.7 ms (tw = 2048
1/(fosc(int)_Low) is used internally for maintaining the IC in an inactive mode during the
supply voltage power-on (see Figure 4 and Figure 5). A deactivation sequence is
performed when:
VREG falls below Vth(VREG)
VDD(INTF) falls below Vth(PORADJ)
VDDP falls below Vth(VDDP)
TDA8035
Product data sheet
COMPANY PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 3.0 — 25 June 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
8 of 31







TDA8035 equivalent, schematic
NXP Semiconductors
TDA8035
High integrated and low power smart card interface
OFFN
PRESN
RST
CLK
I/O
VCC
VUP
Xtal1
Oscint
high frequency
t10 = t11 t12 t13 t14
t15
Fig 10. Emergency deactivation sequence (card extraction)
low frequency
T/2
001aan754
PRESN
OFFN
CMDVCCN
VCC
tdeb
Deactivation caused by
cards withdrawal
Fig 11. Behavior of OFFN, CMDVCCN, PRESN and VCC
tdeb
Deactivation caused by
short circuit
001aan757
TDA8035
Product data sheet
COMPANY PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 3.0 — 25 June 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
16 of 31










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