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PDF ( 数据手册 , 数据表 ) STx5119

零件编号 STx5119
描述 Low-cost interactive set-top box decoder
制造商 STMicroelectronics
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STx5119 数据手册, 描述, 功能
® STx5119
Low-cost interactive set-top box decoder
I Enhanced ST20 32-bit VL-RISC CPU
G 200 MHz, single cycle cache, 4 Kbyte instruction cache,
4 Kbyte data cache, 2 Kbyte SRAM
I Unified memory interface
G up to166 MHz,16-bit wide SDR SDRAM interface
I Programmable flash memory interface
G four separately configurable banks, 8/16-bits wide
G SRAM, peripheral, Flash, SFlash™ support
G support for low-cost DVB-CI
I Programmable transport interface (PTI)
G single transport stream input
G support for DVB transport streams
G integrated DVB, descrambler
I MPEG-2 MP@ML video decoder
G fully programmable horizontal and vertical SRCs
I Graphics/display
G blitter based display compositor
G 8 bpp CLUT graphics, 256 x 30 bits (AYCbCr) CLUT
entries. 16 bpp true color graphics, RGB565, ARGB1555
formats. Link-list control
G 2D paced blitter engine with fill function
ADVANCE DATASHEET
I PAL/NTSC/SECAM encoder
G RGB, CVBS, Y/C and YUV outputs with four 10-bit DAC
outputs. RGB/CVBS or YUV/CVBS or YC/CVBS.
G encoding of CGMS, Teletext, WSS, VPS, close caption
I Audio subsystem
G MPEG-1 layers I/II
G simultaneous MPEG audio decode on audio DACs and
output of Dolby streams on S/PDIF
G IEC958/IEC1937 digital audio output interface
G integrated stereo audio DAC system
I Central DMA controller
I On-chip peripherals
G two ASCs (UARTs) with Tx and Rx FIFOs
G three 8-bit banks of parallel I/O and one 7-bit bank
G one smartcard interface and clock generator
G two SSCs for I2C/SPI master/slave interfaces
G infrared transmitter/receiver
G integrated VCXO
G low-power / RTC / watchdog controller
I JTAG/TAP interface
I Package 24 mm x 24 mm LQFP216
Flash
peripherals
AudioL
AudioR
16
ST20 C1 core 200 MHz
DCU
2K SRAM
Int controller
4K ICache 4K DCache
Audio
Audio DACs
FMI decoder
PCM
player
S/PDIF
S/PDIF
player
Comms peripherals
16
UART (x 2)
IR Tx/Rx GPIO (x 4)
ILC SSCs (x 2)
Comms block
STm5118 interconnect
SDRAM
16
LMI
PTI Clock generation
Reset
System services
FDMA
MP@ML
Video decoder
2D graphics
blitter display
TV out
Video quad DACs
TSIN
Video output
RGB / YC / CVBS
December 2005
7939391A
STMicroelectronics Confidential
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.







STx5119 pdf, 数据表
STx5119
Chapter 39
39.1
39.2
39.3
39.4
39.5
S/PDIF player . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
Audio data mode or encoded mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
Soft reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
Chapter 40
40.1
40.2
S/PDIF player and GPFIFO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
S/PDIF player registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
GPFIFO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
Chapter 41
41.1
41.2
41.3
41.4
41.5
Audio DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
Input signals and output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
Soft mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
Digital and analog power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
Output stage filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
Chapter 42
42.1
42.2
42.3
42.4
Flexible DMA (FDMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
Channel structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
FDMA timing model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
Operating the FDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
Setting up FDMA transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
Chapter 43
43.1
43.2
43.3
43.4
43.5
43.6
43.7
Flexible DMA (FDMA) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
FDMA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
Channel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424
Command mailbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
Interrupt mailbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429
Memory-to-memory moves and paced transfer registers . . . . . . . . . . . . . . . . . . . . . . 431
S/PDIF registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
SCD/PES parsing registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437
Chapter 44
44.1
44.2
Infrared transmitter/receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445
8/543
STMicroelectronics Confidential
7939391A







STx5119 equivalent, schematic
Architecture features
STx5119
3.6 MPEG graphics and display processing
The MPEG graphics and display architecture shown in Figure 4 provides the graphics, video-
stream processing and display capabilities of the STx5119.
Figure 4: Graphics and display subsystem
SDRAM
16
LMI
Blitter
Omega2 interconnect
Omega2
video
decoder
GDMA
DENC
VDAC
Analog
video
out
Video decode
The video decoder is based on the Omega2 cell and provides a memory to memory decode into
YC 4:2:0 macroblock format. It is also able to provide simple resizing based on x2 and x0.5.
3.7 Graphics and display
Display
The STx5119 uses a blitter based display architecture, providing improved graphics and
increased flexibility for building applications as illustrated in Figure 5
The following features are supported:
G SMART GUI,
G Picture in Graphic,
G mosaic channels presentation.
The composition is assisted by the 2D graphic hardware accelerator.
16/543
STMicroelectronics Confidential
7939391A










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