DataSheet8.cn


PDF ( 数据手册 , 数据表 ) XC7VX980T

零件编号 XC7VX980T
描述 Virtex-7 T and XT FPGAs
制造商 Xilinx
LOGO Xilinx LOGO 


1 Page

No Preview Available !

XC7VX980T 数据手册, 描述, 功能
DS183 (v1.21) July 1, 2014
Virtex-7 T and XT FPGAs Data Sheet:
DC and AC Switching Characteristics
Product Specification
Introduction
Virtex®-7 T and XT FPGAs are available in -3, -2, -1, and
-2L speed grades, with -3 having the highest performance.
The -2L devices operate at VCCINT = 1.0V and are screened
for lower maximum static power. The speed specification of
a -2L device is the same as the -2 speed grade. The -2G
speed grade is available in devices utilizing Stacked Silicon
Interconnect (SSI) technology. The -2G speed grade
supports 12.5 Gb/s GTX or 13.1 Gb/s GTH transceivers as
well as the standard -2 speed grade specifications.
Virtex-7 T and XT FPGA DC and AC characteristics are
specified in commercial, extended, industrial, and military
temperature ranges. Except for the operating temperature
range or unless otherwise noted, all the DC and AC
electrical parameters are the same for a particular speed
grade (that is, the timing characteristics of a -1M speed
grade military device are the same as for a -1C speed grade
commercial device). However, only selected speed grades
and/or devices are available in each temperature range.
All supply voltage and junction temperature specifications
are representative of worst-case conditions. The
parameters included are common to popular designs and
typical applications.
Available device and package combinations can be found in:
7 Series FPGAs Overview (DS180)
Defense-Grade 7 Series FPGAs Overview (DS185)
This Virtex-7 T and XT FPGA data sheet, part of an overall
set of documentation on the 7 series FPGAs, is available on
the Xilinx website at www.xilinx.com/7.
DC Characteristics
Table 1: Absolute Maximum Ratings(1)
Symbol
Description
FPGA Logic
VCCINT
VCCAUX
VCCBRAM
VCCO
Internal supply voltage
Auxiliary supply voltage
Supply voltage for the block RAM memories
Output drivers supply voltage for 3.3V HR I/O banks
Output drivers supply voltage for 1.8V HP I/O banks
VCCAUX_IO
VREF
Auxiliary supply voltage
Input reference voltage
I/O input voltage for 3.3V HR I/O banks
VIN(2)(3)(4)
I/O input voltage for 1.8V HP I/O banks
I/O input voltage (when VCCO = 3.3V) for VREF and differential I/O standards except
TMDS_33(5)
VCCBATT
Key memory battery backup supply
GTX and GTH Transceivers
VMGTAVCC
VMGTAVTT
VMGTVCCAUX
VMGTREFCLK
Analog supply voltage for the GTX/GTH transmitter and receiver circuits
Analog supply voltage for the GTX/GTH transmitter and receiver termination circuits
Auxiliary analog Quad PLL (QPLL) voltage supply for the GTX/GTH transceivers
GTX/GTH transceiver reference clock absolute input voltage
Min Max Units
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.40
–0.55
–0.40
1.1
2.0
1.1
3.6
2.0
2.06
2.0
VCCO + 0.55
VCCO + 0.55
2.625
V
V
V
V
V
V
V
V
V
V
–0.5 2.0
V
–0.5 1.1
–0.5 1.32
–0.5 1.935
–0.5 1.32
V
V
V
V
© 2011–2014 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Kintex, Artix, Zynq, Spartan, ISE, Vivado and other designated brands included herein are trademarks of Xilinx in the
United States and other countries. All other trademarks are the property of their respective owners.
DS183 (v1.21) July 1, 2014
Product Specification
www.xilinx.com
Send Feedback
1







XC7VX980T pdf, 数据表
Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics
Power-On/Off Power Supply Sequencing
The recommended power-on sequence is VCCINT, VCCBRAM, VCCAUX, VCCAUX_IO, and VCCO to achieve minimum current
draw and ensure that the I/Os are 3-stated at power-on. The recommended power-off sequence is the reverse of the power-
on sequence. If VCCINT and VCCBRAM have the same recommended voltage levels then both can be powered by the same
supply and ramped simultaneously. If VCCAUX, VCCAUX_IO, and VCCO have the same recommended voltage levels then they
can be powered by the same supply and ramped simultaneously.
For VCCO voltages of 3.3V in HR I/O banks and configuration bank 0:
• The voltage difference between VCCO and VCCAUX must not exceed 2.625V for longer than TVCCO2VCCAUX for each
power-on/off cycle to maintain device reliability levels.
• The TVCCO2VCCAUX time can be allocated in any percentage between the power-on and power-off ramps.
The recommended power-on sequence to achieve minimum current draw for the GTX/GTH transceivers is VCCINT,
VMGTAVCC, VMGTAVTT OR VMGTAVCC, VCCINT, VMGTAVTT. There is no recommended sequencing for VMGTVCCAUX. Both
VMGTAVCC and VCCINT can be ramped simultaneously. The recommended power-off sequence is the reverse of the power-
on sequence to achieve minimum current draw.
If these recommended sequences are not met, current drawn from VMGTAVTT can be higher than specifications during
power-up and power-down.
• When VMGTAVTT is powered before VMGTAVCC and VMGTAVTT – VMGTAVCC > 150 mV and VMGTAVCC < 0.7V, the
VMGTAVTT current draw can increase by 460 mA per transceiver during VMGTAVCC ramp up. The duration of the current
draw can be up to 0.3 x TMGTAVCC (ramp time from GND to 90% of VMGTAVCC). The reverse is true for power-down.
• When VMGTAVTT is powered before VCCINT and VMGTAVTT – VCCINT > 150 mV and VCCINT < 0.7V, the VMGTAVTT current
draw can increase by 50 mA per transceiver during VCCINT ramp up. The duration of the current draw can be up to
0.3 x TVCCINT (ramp time from GND to 90% of VCCINT). The reverse is true for power-down.
There is no recommended sequence for supplies not shown.
DS183 (v1.21) July 1, 2014
Product Specification
www.xilinx.com
Send Feedback
8







XC7VX980T equivalent, schematic
Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics
Table 18: Maximum Physical Interface (PHY) Rate for Memory Interfaces IP available with the Memory Interface
Generator(1)(2)
Speed Grade
Memory Standard
I/O Bank Type VCCAUX_IO
-3
-2/-2L/-2G
-1
Units
-1M
4:1 Memory Controllers
HP
2.0V
1866(3)
1866(3)
1600
1066
DDR3
HP
1.8V
1600
1333
1066
800 Mb/s
HR
N/A
1066
1066
800
800
HP
2.0V
1600
1600
1333
1066
DDR3L
HP
1.8V
1333
1066
800
800 Mb/s
HR N/A 800 800 667 N/A
DDR2
HP 2.0V
667
HP
1.8V
800
800
800
Mb/s
HR N/A
533
RLDRAM III
HP
2.0V
800
667
667
550
MHz
HP
1.8V
550
500
450
400
HR N/A
N/A
2:1 Memory Controllers
HP 2.0V
DDR3
HP
1.8V
1066
1066
800
667 Mb/s
HR N/A
DDR3L
HP 2.0V
1066
1066
800
667
HP 1.8V
Mb/s
HR N/A 800 800 667 N/A
DDR2
HP 2.0V
667
HP
1.8V
800
800
800
Mb/s
HR N/A
533
QDR II+(4)
HP 2.0V
550 500 450 300
HP 1.8V
MHz
HR N/A 500 450 400 300
HP 2.0V
RLDRAM II
HP
1.8V
533
500
450
400 MHz
HR N/A
HP 2.0V
LPDDR2
HP
1.8V
667
667
667
533 Mb/s
HR N/A
Notes:
1. VREF tracking is required. For more information, see the 7 Series FPGAs Memory Interface Solutions User Guide (UG586).
2. When using the internal VREF, the maximum data rate is 800 Mb/s (400 MHz).
3. File a WebCase for designs over 1800 Mb/s.
4. The maximum QDRII+ performance specifications are for burst-length 4 (BL = 4) implementations. Burst length 2 (BL = 2) implementations
are limited to 333 MHz for all speed grades and I/O bank types.
DS183 (v1.21) July 1, 2014
Product Specification
www.xilinx.com
Send Feedback
16










页数 30 页
下载[ XC7VX980T.PDF 数据手册 ]


分享链接

Link :

推荐数据表

零件编号描述制造商
XC7VX980TVirtex-7 T and XT FPGAsXilinx
Xilinx

零件编号描述制造商
STK15C88256-Kbit (32 K x 8) PowerStore nvSRAMCypress Semiconductor
Cypress Semiconductor
NJM4556DUAL HIGH CURRENT OPERATIONAL AMPLIFIERNew Japan Radio
New Japan Radio
EL1118-G5 PIN LONG CREEPAGE SOP PHOTOTRANSISTOR PHOTOCOUPLEREverlight
Everlight


DataSheet8.cn    |   2020   |  联系我们   |   搜索  |  Simemap